1. Field of the Invention
The present invention relates in general to a transistor structure for an electrostatic discharge (ESD) protection circuit and, more particularly, to an ESD protection device having improved performance.
2. Description of the Related Art
Metal oxide semiconductor (MOS) integrated circuits (ICs) receive input signals through the gate of a MOS transistor. If a high voltage input signal is applied to the gate terminal, the gate oxide layer may be unable to withstand the high voltage and break down. Higher than normal input voltages may be produced when semiconductor devices are transported by humans or machines. However, the sources of abnormally high voltages are many. For example, electric charges can be produced by friction between surfaces or when an IC is unpacked from plastic packaging. Static electricity can range from several hundreds volts to several thousand volts. If such high voltages are applied to the pins of an IC package, voltage breakdown of the gate oxide layer of a transistor within the package can occur which would result in the transistor being inoperative. As a result, the entire IC could be rendered inoperative.
To prevent such damages to the MOS transistors, protective circuits are connected to pins of an IC package. Such protective circuits are typically connected between each input/output (I/O) pad and the integrated circuit. The protective circuits are designed to conduct when a high voltage is applied to the I/O pad. Hence, these protective circuits provide an electrical path to, e.g., ground, to safely discharge the high voltage.
As feature sizes of semiconductor IC devices are reduced to the sub-micron level, one of the design rules for making high-speed ICs is to use self-aligned suicide (salicide) fabrication procedures to make MOS transistor components. The goal is to effectively reduce the sheet resistance in the source/drain regions, so that the fabricated MOS transistors operate at higher speeds. However, the use of salicides for high-speed device circuits results in the problem of maintaining adequate ESD protection for such circuits in these IC devices. If the ESD protection circuits are also implemented in the same salicide fabrication technology, then the sheet resistance in the N+ diffusion regions for the ESD protection circuits will fall from the traditional range of about 60Ω per-square for effective protection to about 2-3Ω per-square.
FIG. 1 is a reproduction of FIG. 4 of U.S. Pat. No. 5,742,083 which illustrates the layout of an ESD protection circuit. The ESD circuit shown in FIG. 1 includes an MOS transistor that includes field oxide islands 40a-40g that extend from a drain diffusion region 42 in the transistor drain side into the source side. Field oxide islands 40a-40g pass underneath a strip-shaped gate structure 41, but do not extend to a metallization overlying and connected to the drain diffusion region via contact openings 43a-43g. Islands 40a-40g serve to segment part of drain diffusion region 42, into segmented regions 42a-42g, across which current flows during an ESD event. This arrangement serves to partially distribute current during an ESD event which can improve ESD protection.
While the arrangement in FIG. 1 provides some improvement in ESD protection, further improvement is desirable.